Processors (e.g., microprocessors, CPUs, etc.) are used in a wide variety of products and applications, from desktop computers to portable electronic devices, such as cellular phones, laptop computers, and PDAs (personal digital assistants). Some processors are extremely powerful (e.g., processors in high-end computer workstations), while other processors have a simpler design, for lower-end, less expensive applications and products.
There is a general dichotomy between performance and power. Generally speaking, high-performance processors having faster operation and/or more complex designs tend to consume more power than their lower-performance counterparts. Higher power consumption generally leads to higher operating temperatures and shorter battery life (for devices that operate from battery power). The ever-increasing demand and use of portable electronic devices is driving a demand to produce processors that realize lower-power operation, while at the same time maintaining satisfactory performance levels.
One method for reducing the power consumption of devices is to provide modes of reduced-power operation (sometimes referred to as “sleep states”) when the devices (or certain portions thereof) are not in use. However, there is also a desire to reduce the power consumption of devices even during active operation. This is often accomplished by providing more efficient designs to the operational components of the devices.
There are a number of power-consuming components in various electronic devices, and the processor is one of them. Even within a processor, there are a number of functional sections, and decoder logic is one such area. The decoder logic of a processor decodes an encoded instruction into a number electrical signals for controlling and carrying out the function of the instruction within execution logic provided in the processor. FIG. 1 is a block diagram illustrating a processor design, which includes a decode stage.
Processor circuitry, however, has certain drawbacks. More specifically, when the word length in an instruction changes from one length to another, excessive power is dissipated due to the parallel structure of multiple instruction decoders. For each length word and computer language the processor is configured to handle, the processor utilizes a separate decoder. When the instruction is loaded into decode stage, each instruction decoder attempts to decode the instruction. With each instruction decoder trying to decode the same instruction, excessive power is dissipated and battery life is shortened.
Accordingly, there is a heretofore unaddressed need to overcome the deficiencies and shortcomings described above.